EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 406

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

13–8
Figure 13–5. IEEE Std. 1149.1 TAP Controller State Machine
Stratix III Device Handbook, Volume 1
TMS = 1
TMS = 0
When the TAP controller is in the TEST_LOGIC/RESET state, the BST circuitry is
disabled, the device is in normal operation, and the instruction register is initialized
with IDCODE as the initial instruction. At device power-up, the TAP controller starts
in this TEST_LOGIC/RESET state. In addition, forcing the TAP controller to the
TEST_LOGIC/RESET state is achieved by holding TMS high for five TCK clock cycles,
or by holding the TRST pin low. In the TEST_LOGIC/RESET state, the TAP controller
remains in this state as long as TMS is held high (while TCK is clocked) or TRST is held
low.
TEST_LOGIC/
Figure 13–6
RUN_TEST/
RESET
IDLE
TMS = 0
TMS = 1
shows the timing requirements for the IEEE Std. 1149.1 signals.
TMS = 1
TMS = 1
TMS = 0
TMS = 0
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 1
CAPTURE_DR
UPDATE_DR
PAUSE_DR
SHIFT_DR
EXIT1_DR
EXIT2_DR
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
TMS = 0
SELECT_DR_SCAN
TMS = 0
TMS = 0
TMS = 1
TMS = 1
TMS = 1
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 0
TMS = 1
TMS = 1
CAPTURE_IR
UPDATE_IR
PAUSE_IR
EXIT1_IR
EXIT2_IR
SHIFT_IR
SELECT_IR_SCAN
IEEE Std. 1149.1 BST Operation Control
TMS = 0
TMS = 0
TMS = 0
TMS = 1
© July 2010 Altera Corporation