EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 403

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
IEEE Std. 1149.1 Boundary-Scan Register
Boundary-Scan Cells of a Stratix III Device I/O Pin
Figure 13–4. Stratix III Device's User I/O BSC with IEEE Std. 1149.1 BST Circuitry
© July 2010
To or From
Circuitry
I/O Cell
and/or
Device
Logic
Array
Altera Corporation
OUTJ
OEJ
The Stratix III device three-bit boundary-scan cell (BSC) consists of a set of capture
registers and a set of update registers. The capture registers can connect to internal
device data through the OUTJ, OEJ, and PIN_IN signals, while the update registers
connect to external data through the PIN_OUT and PIN_OE signals.
The global control signals for the IEEE Std. 1149.1 BST registers (such as shift,
clock, and update) are generated internally by the TAP controller. The MODE signal
is generated by a decode of the instruction register. The HIGHZ signal is high when
executing the HIGHZ instruction. The data signal path for the boundary-scan register
runs from the serial data in (SDI) signal to the serial data out (SDO) signal. The scan
register begins at the TDI pin and ends at the TDO pin of the device.
Figure 13–4
INJ
SDI
shows the Stratix III device's user I/O boundary-scan cell.
0
1
0
1
0
1
SHIFT
D
D
D
OUTPUT
CLOCK
Registers
Capture
INPUT
OE
Q
Q
Q
SDO
D
D
UPDATE
Registers
D
OUTPUT
INPUT
Update
OE
Q
Q
Q
HIGHZ
V
CC
0
1
MODE
0
1
0
1
0
1
Signals
Global
Stratix III Device Handbook, Volume 1
PIN_OUT
PIN_OE
PIN_IN
Output
Buffer
Pin
13–5