EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 365
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 11: Configuring Stratix III Devices
Passive Serial Configuration
Table 11–10. PS Timing Parameters for Stratix III Devices (Part 2 of 2)
PS Configuration Using a Microprocessor
PS Configuration Using a Download Cable
© March 2011 Altera Corporation
t
t
t
t
Notes to
(1) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.
Symbol
CD2UM
CD2C U
CD2UM C
Table
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
f
f
11–10:
1
Device configuration options and how to create configuration files are discussed
further in the
volume 2 of the Configuration Handbook.
In this PS configuration scheme, a microprocessor can control the transfer of
configuration data from a storage device, such as flash memory, to the target Stratix III
device.
You can do a PS configuration using MicroBlaster™ Passive Serial Software Driver.
For more information, refer to
Software
For all configuration and timing information, refer to
MAX II Device as an External Host” on page
when using a microprocessor as an external host.
In this section, the generic term download cable includes the Altera USB-Blaster USB
port download cable, MasterBlaster™ serial/USB communications cable,
ByteBlaster II parallel port download cable, ByteBlasterMV™ parallel port download
cable, and the EthernetBlaster download cable.
In PS configuration with a download cable, an intelligent host (such as a PC) transfers
data from a storage device to the device by using the USB-Blaster, MasterBlaster,
ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable.
Driver.
Parameter
Device Configuration Options
(2)
AN423: Configuring the MicroBlaster Passive Serial
and
(4,436 × CLKUSR period)
11–27. This section is also applicable
Configuration File
4 × maximum
DCLK period
tCD2CU +
Minimum
“PS Configuration Using a
—
20
Stratix III Device Handbook, Volume 1
Formats chapters in
Maximum
100
40
—
—
Units
11–33
ns
—
—
μs
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