EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 242

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

7–38
Figure 7–27. RSDS I/O Standard Termination for Stratix III Devices
Notes to
(1) R
(2) Column and row I/O banks support RSDS_E_1R and RSDS_E_3R I/O standards using two single-ended output buffers.
Stratix III Device Handbook, Volume 1
Termination
Termination
On-Board
External
OCT
P
=120 Ω for RSDS_E_1R, R
Figure
f
7–27:
Transmitter
Transmitter
A resistor network is required to attenuate the LVDS output-voltage swing to meet the
RSDS specifications. You can modify the three-resistor network values to reduce
power or improve the noise margin. The resistor values chosen should satisfy
Equation
Equation 7–1.
Altera recommends that you perform additional simulations using IBIS models to
validate that custom resistor values meet the RSDS requirements.
For more information about the RSDS I/O standard, refer to the RSDS Specification
from the
Mini-LVDS
The row I/O banks support mini-LVDS output using true LVDS output buffers
without an external resistor network. The column I/O banks support mini-LVDS
output using two single-ended output buffers with the external one- or three-resistor
network, as shown in
One-Resistor Network (RSDS_E_1R)
P
=170 Ω , and R
≤1 inch
≤1 inch
National Semiconductor
7–1:
R P
R P
S
=120 Ω for RSDS_E_3R.
50 Ω
50 Ω
50 Ω
50 Ω
Figure
100 Ω
100 Ω
Stratix III OCT
Receiver
Receiver
7–28.
website.
Rs
------------------- -
Rs
(Note
×
+
Rp
----- -
Rp
----- -
2
2
Transmitter
1),
Transmitter
=
(2)
50Ω
Three-Resistor Network (RSDS_E_3R)
Chapter 7: Stratix III Device I/O Features
R S
R S
R S
≤1 inch
R S
≤
1 inch
Termination Schemes for I/O Standards
R P
R P
© July 2010 Altera Corporation
50
50 Ω
50
50 Ω
100 Ω
100
Stratix III OCT
Ω
Receiver
Receiver