EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 429

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 14: Design Security in Stratix III Devices
Supported Configuration Schemes
Table 14–4. Allowed Configuration Modes for Various Security Modes
© May 2009 Altera Corporation
Secure in tamper
resistant mode using
non-volatile key with
tamper protection set
Note to
(1) There is no impact to the configuration time required compared to unencrypted configuration modes except fast passive parallel with AES
(and/or decompression) which requires DCLK of 4× the data rate.
Security Mode
Table
14–4:
1
The design security feature with encrypted configuration file is available in all
configuration methods, except JTAG. Therefore, use the design security feature in FPP
mode (when using external controller, such as a MAX II device or a microprocessor
and a flash memory), or in fast AS and PS configuration schemes.
Table 14–5
feature both for volatile and non-volatile key programming.
Table 14–5. Design Security Configuration Schemes Availability
Use the design security feature with other configuration features, such as compression
and remote system upgrade features. When you use compression with the design
security feature, the configuration file is first compressed and then encrypted using
the Quartus II software. During configuration, the Stratix III device first decrypts and
then decompresses the configuration file.
FPP
Fast AS
PS
JTAG
Notes to
(1) In this mode, the host system must send a DCLK that is 4× the data rate.
(2) JTAG configuration supports only unencrypted configuration file.
Encrypted
Configuration
Configuration Scheme
(2)
Table
File
summarizes the configuration schemes that support the design security
14–5:
■
■
■
■
Passive serial with AES (and/or with decompression)
Fast passive parallel with AES (and/or with decompression)
Remote update fast AS with AES (and/or with decompression)
Fast AS (and/or with decompression)
MAX II device or
microprocessor and flash
memory
Serial configuration device
MAX II device or
microprocessor and flash
memory
Download cable
MAX II device or
microprocessor and flash
memory
Download cable
Configuration Method
Allowed Configuration Modes
(Note 1)
(Part 2 of 2)
Stratix III Device Handbook, Volume 1
Design Security
v
v
v
v
—
(1)
14–7