EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 115
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 5: DSP Blocks in Stratix III Devices
DSP Block Resource Descriptions
DSP Block Resource Descriptions
Figure 5–6. Half-DSP Block Architecture
Notes to
(1) chainin[] can only come from the chainout port of the previous DSP blocks and not from general routing.
(2) Block output for accumulator overflow and saturate overflow.
(3) Block output for saturation overflow of chainout.
(4) When the chainout adder is not in use, the second adder register banks are known as output register banks.
© March 2010 Altera Corporation
datab_2[ ]
datab_3[ ]
datab_1[ ]
dataa_2[ ]
dataa_3[ ]
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
Figure
chainin[ ] (1)
scanina[ ]
5–6:
loopback
scanouta
The DSP block consists of the following elements:
■
■
■
■
■
■
A detailed overall architecture of the top half of the DSP block is shown in
clock[3..0]
ena[3..0]
alcr[3..0]
Input register bank
Four Two-Multiplier Adders
Pipeline register bank
Two second-stage adders
Four round and saturation logic units
Second adder register and output register bank
Half-DSP Block
chainout_saturate
chainout_round
zero_loopback
zero_chainout
accum_sload
output_saturate
output_round
(4)
shift_right
rotate
signa
signb
chainout
Stratix III Device Handbook, Volume 1
overflow (2)
chainout_sat_overflow (3)
result[ ]
Figure
5–6.
5–9
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