EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 229
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 7: Stratix III Device I/O Features
OCT Support
Figure 7–11. Dynamic Parallel OCT in Stratix III Devices
© July 2010
Receiver
Altera Corporation
50
f
Transmitter
50
Stratix III OCT
Dynamic OCT
Stratix III devices support on-off dynamic series and parallel termination for a
bi-directional I/O in all I/O banks.
supported in the Stratix III device. Dynamic parallel termination is enabled only
when the bi-directional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bi-directional I/O acts
as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bi-directional path because the signal integrity is
optimized depending on the direction of the data.
You should connect a bi-directional pin that uses both 25-Ω or 50-Ω series termination
and 50-Ω input termination to a calibration block that has a 50-Ω external resistor
connected to its RUP and RDN pins. The 25-Ω series termination on the bi-directional
pin is achieved through internal divide by two circuits.
For more information about tolerance specifications for OCT with calibration, refer to
the
Stratix III OCT
V
GND
DC and Switching Characteristics of Stratix III Devices
CCIO
V
GND
CCIO
100
100
100
100
Z
Z
O
O
= 50
= 50
Figure 7–11
100
100
100
100
shows the termination schemes
V
VCCIO
GND
GND
CCIO
Stratix III OCT
Stratix III OCT
chapter.
Transmitter
Stratix III Device Handbook, Volume 1
Receiver
50
50
7–25
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