EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 329
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 10: Hot Socketing and Power-On Reset in Stratix III Devices
Power-On Reset Specifications
Power-On Reset Specifications
© March 2010
Altera Corporation
1
Figure 10–3. Simplified POR Block Diagram
The ramp-up time specification for Stratix III devices is listed in
Table 10–1. Power Supplies Ramp-Up Time (t
The POR circuit monitors the power supplies listed in
Table 10–2. Power Supplies Monitored by the POR Circuitry
To ensure proper device operation, all power supplies listed in
to be powered up at all times during device operation.
V
V
V
V
V
V
V
V
V
C CP T
C C
C CIO
C C_C LK IN
C C
C CL
C CP T
C CP D
C CP GM
, V
Power Supply
, V
Power Supply
C CL
CC A_P LL
, V
C CPD
, V
, V
C CD_P LL
C CP GM
VCC
VCCL
PORSEL
VCCPT
VCCPGM
VCCPD
,
,
I/O registers power supply
Selectable core voltage power supply
Power supply for the programmable power
technology
I/O pre-driver power supply
Configuration pins power supply
Regulator POR
Satellite POR
PORSEL setting
Main POR
HIGH
HIGH
GND
GND
Description
RAMP
) Requirements
Minimum
50
50
50
50
μs
μs
μs
μs
Table
POR PULSE
SETTING
Ramp-up Time
Stratix III Device Handbook, Volume 1
10–2.
Table 10–2
Table
0.9, 1.1
1.1
2.5
2.5, 3.0, 3.3
1.8, 2.5, 3.0, 3.3
POR
10–1.
Setting (V)
Maximum
100 ms
12 ms
5 ms
5 ms
are required
10–5
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