EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 178

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

6–30
Figure 6–29. External Feedback Mode in Stratix III Devices
Stratix III Device Handbook, Volume 1
inclk
Figure 6–28
mode.
Figure 6–28. Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode
Note to
(1) The internal PLL clock output can lead or lag the external PLL clock outputs.
External Feedback Mode
In external feedback (EFB) mode, the external feedback input pin (fbin) is
phase-aligned with the clock input pin, as shown in
allows you to remove clock delay and skew between devices. This mode is supported
on all Stratix III PLLs.
In this mode, the output of the M counter (FBOUT) feeds back to the PLL fbin input
(using a trace on the board) becoming part of the feedback loop. Also, you can use one
of the dual-purpose external clock outputs as the fbin input pin in EFB mode.
When using this mode, you must use the same I/O standard on the input clock,
feedback input, and output clocks. Left/Right PLLs support EFB mode when using
single-ended I/O standards only.
Stratix III devices.
High-bandwidth PLL settings are not supported in external feedback mode. Select a
”low“ or “medium” PLL bandwidth in the ALTPLL MegaWizard Plug-In Manager
when using PLLs in external feedback mode.
÷n
Figure
6–28:
shows an example waveform of the PLL clocks' phase relationship in ZDB
Register Clock Port
Clock Outputs (1)
PLL Clock at the
PFD
Dedicated PLL
PLL Reference
Clock at the
Input Pin
CP/LF
Phase Aligned
VCO
Figure 6–29
÷C0
÷C1
÷m
Chapter 6: Clock Networks and PLLs in Stratix III Devices
shows the EFB mode implementation in
fbout
fbin
Figure
PLL_<#>_CLKOUT#
6–30. Aligning these clocks
PLL_<#>_CLKOUT#
© July 2010 Altera Corporation
external
board
trace
PLLs in Stratix III Devices