EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 259

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

Chapter 8: External Memory Interfaces in Stratix III Devices
Memory Interfaces Pin Support
Figure 8–6. Number of DQS/DQ Groups per Bank in EP3SL200, EP3SE260 and EP3SL340 Devices in the 1517-pin FineLine
BGA Package
Notes to
(1) You can also use DQS/DQSn pins in some of the ×4 groups as RUP/RDN pins. You cannot use a ×4 group for memory interfaces if two pins of
(2) Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are not going to be used by your
(3) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) and eight
© March 2010 Altera Corporation
42 User I/Os (3)
42 User I/Os (3)
I/O Bank 1A (1)
50 User I/Os (3)
I/O Bank 1C (2)
I/O Bank 2A (1)
50 User I/Os (3)
I/O Bank 1B
24 User I/Os
I/O Bank 2B
I/O Bank 2C
24 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
the group are being used as RUP and RDN pins for OCT calibration. You can still use the ×16/×18 or ×32/×36 groups that includes these ×4 groups.
However, there are restrictions on using ×8/×9 groups that include these ×4 groups as described on
configuration scheme.
dedicated corner PLL clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn,
PLL_R1_CLKp, and PLL_R1_CLKn) that can be used for data inputs.
x8/x9=3
x8/x9=2
x8/x9=2
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
x8/x9=3
x4=6
DLL1
x4=4
x4=6
x4=4
DLL0
x4=7
x4=7
Figure
8–6:
I/O Bank 8A (1)
I/O Bank 3A (1)
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
I/O Bank 8B
I/O Bank 3B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
EP3SL200, EP3SE260, and EP3SL340 Devices
I/O Bank 3C
I/O Bank 8C
32 User I/Os
32 User I/Os
x16/x18=0
x32/x36=0
x16/x18=0
x32/x36=0
x8/x9=1
x8/x9=1
x4=3
x4=3
1517-Pin FineLine BGA
(1)
(1)
I/O Bank 7C
32 User I/Os
I/O Bank 4C
32 User I/Os
x16/x18=0
x32/x36=0
x16/x18=0
x32/x36=0
x8/x9=1
x8/x9=1
x4=3
x4=3
I/O Bank 7B
I/O Bank 4B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
page
Stratix III Device Handbook, Volume 1
8–5.
I/O Bank 7A (1)
I/O Bank 4A (1)
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
42 User I/Os (3)
42 User I/Os (3)
50 User I/Os (3)
I/O Bank 6A (1)
I/O Bank 5A (1)
I/O Bank 6C
50 User I/Os (3)
I/O Bank 5C
24 User I/Os
I/O Bank 5B
I/O Bank 6B
24 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=2
x8/x9=3
x8/x9=2
x4=6
x8/x9=3
x4=6
x4=4
DLL2
x4=7
x4=4
DLL3
x4=7
8–11