EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 52

• Manufacturer Part Number: EP3SL150F1152C2N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2409; EP3SL150F1152C2NES

2–8
ALM Operating Modes
Stratix III Device Handbook, Volume 1
1
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register output can drive these output drivers (refer to
Figure
or direct link routing connections, and one of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output while the
register drives another output.
This feature, called register packing, improves device utilization because the device
can use the register and the combinational logic for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT of the same
ALM so that the register is packed with its own fan-out LUT. This provides another
mechanism for improved fitting. The ALM can also drive out registered and
unregistered versions of the LUT or adder output.
The Stratix III ALM can operate in one of the following modes:
■
■
■
■
■
Each mode uses ALM resources differently. In each mode, eleven available inputs to
an ALM—the eight data inputs from the LAB local interconnect, carry-in from the
previous ALM or LAB, the shared arithmetic chain connection from the previous
ALM or LAB, and the register chain connection—are directed to different destinations
to implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, synchronous clear, synchronous load, and clock enable control for
the register. These LAB-wide signals are available in all ALM modes.
Refer to
control signals.
The Quartus II software and supported third-party synthesis tools, in conjunction
with parameterized functions such as the library of parameterized modules (LPM)
functions, automatically choose the appropriate mode for common functions such as
counters, adders, subtractors, and arithmetic functions.
Normal Mode
The normal mode is suitable for general logic applications and combinational
functions. In this mode, up to eight data inputs from the LAB local interconnect are
inputs to the combinational logic. The normal mode allows two functions to be
implemented in one Stratix III ALM, or an ALM to implement a single function of up
to six inputs. The ALM can support certain combinations of completely independent
functions and various combinations of functions that have common inputs.
shows the supported LUT combinations in normal mode.
Normal
Extended LUT Mode
Arithmetic
Shared Arithmetic
LUT-Register
2–6). For each set of output drivers, two ALM outputs can drive column, row,
“LAB Control Signals” on page 2–4
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
for more information on the LAB-wide
© February 2009 Altera Corporation
Adaptive Logic Modules
Figure 2–7