Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 103
![IC 8MHZ Z8500 CMOS SCC 44-PLCC](/photos/6/57/65795/269-44-plcc_sml.jpg)
Z85C3008VSG
Manufacturer Part Number
Z85C3008VSG
Description
IC 8MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3008VSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
44
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3932
Z85C3008VSG
Z85C3008VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z85C3008VSG
Manufacturer:
Zilog
Quantity:
800
Company:
Part Number:
Z85C3008VSG
Manufacturer:
MAX
Quantity:
74
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SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
4-28
Interface
to SCC
RR1
In SDLC Mode the following definitions apply.
- All Sent bypasses MUX and equals contents of SCC Status Register.
- Parity Bits bypasses MUX and does the same.
- EOF is set to 1 whenever reading from the FIFO.
2 Bits
Overrun, CRC Error
6-Bit MUX
5 Bits
SCC Status Reg
Residue Bits(3)
Figure 4-15. SDLC Frame Status FIFO (N/A on NMOS)
6 Bits
RR1
10 Deep by 19 Bits Wide
5 Bits
Bit 7
FIFO Array
EOF = 1
RR7 D7
FIFO Overflow Status Bit
MSB pf RR(7) is set on Status FIFO overflow
Bit 6
Frame Status FIFO Circuitr
RR7 D6
FIFO Data available status bit Status Bit set to 1
When reading from FIFO.
Bits 5-0
Byte Counter
6 Bits
RR7 D5-D0 + RR6 D7 - D0
Byte Counter Contains 14 bits
for a 16 KByte maximum count.
14 Bits
RR6
8 Bits
EN
End of Frame Signal
Status Read Comp
Reset on Flag Detect
Increment on Byte DET
Enable Count in SDLC
Over
4-Bit Comparator
Head Pointer
4-Bit Counter
4-Bit Counter
Tail Pointer
Equal
WR(15) Bit 2
Set Enables
Status FIFO
FIFO Enable
UM010901-0601
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