Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 139
![IC 8MHZ Z8500 CMOS SCC 44-PLCC](/photos/6/57/65795/269-44-plcc_sml.jpg)
Z85C3008VSG
Manufacturer Part Number
Z85C3008VSG
Description
IC 8MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3008VSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
44
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3932
Z85C3008VSG
Z85C3008VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z85C3008VSG
Manufacturer:
Zilog
Quantity:
800
Company:
Part Number:
Z85C3008VSG
Manufacturer:
MAX
Quantity:
74
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Application Note
Interfacing Z80
PERIPHERAL INTERRUPT OPERATION
Understanding peripheral interrupt operation requires a
basic knowledge of the Interrupt Pending (IP) and Interrupt
Under Service (IUS) bits in relation to the daisy chain. Both
Z80 and Z8500 peripherals are designed in such a way
that no additional interrupts can be requested during an
Interrupt Acknowledge cycle. This allows that interrupt
daisy chain to settle, and ensures proper response of the
interrupting device.
The IP bit is set in the peripheral when CPU intervention is
required (such conditions as buffer empty, character
available, error detection, or status changes). The
Interrupt Acknowledge cycle does not necessarily reset
the IP bit. This bit is cleared by a software command to the
peripheral, or when the action that generated the interrupt
6-4
®
CPUs to the Z8500 Peripheral Family
Figure 3. Z8500 Interrupt State Diagram
is completed (i.e., reading a character, writing data,
resetting errors, or changing the status). When the
interrupt has been serviced, other interrupts can occur.
The
Acknowledge) for recognition of an Interrupt Acknowledge
cycle. This pin, used in conjunction with /RD, allows the
Z8500 peripheral to gate its interrupt vector onto the data
bus. An active /RD signal during an Interrupt Acknowledge
cycle performs two functions. First, it allows the highest
priority device requesting an interrupt to place its interrupt
vector on the data bus. Secondly, it sets the IUS bit in the
highest priority device to indicate that the device is
currently under service.
Z8500
peripherals
use
/INTACK
UM010901-0601
(Interrupt
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