Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 310

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

UM010901-0601
Q. Does Valid Access Recovery Time affect the inter-
A. No. The interrupt vector is put on the bus by the SCC
INTERRUPT CONSIDERATIONS
Q. What conditions must exist for the SCC to gener-
A. Interrupts must be enabled (MIE = 1 and IE = 1). The
Q. How can the /INTACK signal be synchronized with
A. /INTACK needs to be synchronized with PCLK. This
Q. Is /CE required during an Interrupt Acknowledge
A. No.
Q. How long does /INT stay active low when request-
A. If the SCC is operated in a polled mode, the /INT will
Q. Can you use the SCC without a hardware interrupt
A. Yes. If you are not using the hardware daisy chain, you
Q. How do you acknowledge an interrupt without a
A. Reset the responsible interrupt pending bit (IP). The
Q. When are the IP bits cleared?
A. A transmitter empty IP is cleared by writing to the
cycle?
ing an interrupt?
acknowledge?
hardware interrupt acknowledge?
rupt acknowledge cycle?
during the interrupt acknowledge cycle, but does not
require any recovery time.
ate an interrupt request?
Interrupt Enable Input (IEI) must be high. The interrupt
pending bit (IP) must be set and its interrupt under ser-
vice bit (IUS) must be reset. No interrupt acknowledge
cycle may be active.
PCLK?
can be accomplished by changing /INTACK only on
the falling edge of PCLK by using a D flip-flop that is
clocked with the inverted PCLK.
remain active until the IP bit is reset. For an interrupt
acknowledge cycle, the /INT will go inactive shortly af-
ter the falling edge of /RD or /DS when the IUS bit is
set.
don’t need to give an interrupt acknowledge. Tie the
intack pin high, enable interrupts, and on responding
to an interrupt, check RR3 for the cause, and special
receive conditions if you are in receive mode. The in-
ternal daisy-chain settling time must still be met. (IEI to
IEO delay time specification.)
/INT line follows the IP bit.
data register. A receive character available IP is
cleared by reading the data register. The exter-
Q. Why can some systems violate the recovery time
A. This violation may or may not matter to the SCC. This
Q. Can the IP bits be set while the SCC is servicing
A. Yes. If the interrupting condition has a higher priority
Q. Can the IUS bits be accessed?
A. No. They are not accessible.
Q. When do IUS bits get set?
A. The IUS bits are set during an interrupt acknowledge
Q. How do you reset interrupts on the SCC?
A. The interrupt under service bit (IUS) can be reset by
Q. Why is the interrupt daisy chain settle time re-
A. This mechanism allows the peripheral with the highest
Q. Is there still a settle time if the peripherals are not
A. Even if only one SCC is used, there still is a minimum
Q. How should the vectors be read when utilizing the
A. /INTACK should be tied to 5 volts through a register.
Q. How is the vector register different from the other
A. The vector register is shared between both channels.
by 1 or 2 PCLK’s without affecting the data to the
SCC?
phase relationship between PCLK, /RD, /WR, (/AS,
/DS for Z8030) can by ASYNC. The SCC requires
some time internally to synchronize these signals. The
electrical specs for the SCC indicate a recovery time,
which is the worst case maximum.
nal/status interrupt IP is cleared by the command Re-
set Ext/Status Interrupts.
other interrupts?
than the interrupt currently being serviced, it causes
another interrupt, thus nesting the interrupt services.
cycle on the falling edge or /RD or /DS.
the command “Reset Highest IUS” or 38 Hex to WR0.
Reset Highest IUS should be the last command issued
in the interrupt service routine.
quired?
priority interrupt pending in the hardware interrupt dai-
sy chain to have its interrupt serviced.
chained?
daisy-chain settle time due to the internal chain.
/INTACK?
Erroneous reads can result from a floating INTACK.
The interrupt vectors can be read after an interrupt
from RR2.
registers?
The Write register can be accessed from either chan-
nel. Reading “Read Register 2” on Channel A (RR2A)
returns the unmodified vector, and RR2B returns the
SCC™/ESCC™ User’s Manual
Zilog SCC
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