Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 28

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

UM010901-0601
2.2.7 Z80X30 Reset
The Z80X30 may be reset by either a hardware or software
reset. Hardware reset occurs when /AS and /DS are both
Low at the same time, which is normally an illegal condi-
tion. As long as both /AS and /DS are Low, the Z80X30
recognizes the reset condition. However, once this condi-
tion is removed, the reset condition is asserted internally
for an additional four to five PCLK cycles. During this time,
any attempt to access is ignored.
WR0
WR1
WR2
WR3
WR4
WR5
WR6
WR7
WR7'*
WR9
WR10
WR11
WR12
WR13
WR14
WR15
RR0
RR1
RR3
RR10
Notes:
*WR7' is available only on the Z80230.
X
X
X
X
X
X
X
X
X
7
0
0
0
0
1
0
0
1
0
0
0
X
X
X
X
X
X
X
X
X
X
6
0
0
0
1
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
5
0
1
0
0
0
1
1
0
0
0
Hardware RESET
X
X
X
X
X
X
X
X
4
0
0
0
0
0
0
0
1
1
0
0
0
X
X
X
X
X
X
X
X
3
0
0
0
0
0
0
1
0
1
0
0
0
Table 2-4. Z80X30 Register Reset Values
X
X
X
X
X
X
X
2
0
1
0
0
0
0
0
0
0
1
1
0
0
X
X
X
X
X
X
X
X
1
0
0
0
0
0
0
0
0
0
1
0
0
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
The Z80X30 has three software resets that are encoded
into two command bits in WR9. There are two channel re-
sets, which only affect one channel in the device and
some bits of the write registers. The command forces the
same result as the hardware reset, the Z80X30 stretches
the reset signal an additional four to five PCLK cycles be-
yond the ordinary valid access recovery time. The bits in
WR9 may be written at the same time as the reset com-
mand because these bits are affected only by a hardware
reset. The reset values of the various registers are shown
in Table 2-4.
X
X
X
X
X
X
X
X
X
X
X
7
0
0
0
0
0
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
6
0
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
5
0
1
0
1
1
0
0
0
Channel RESET
SCC™/ESCC™ User’s Manual
X
X
X
X
X
X
X
X
X
X
4
0
0
0
0
0
0
1
0
0
0
Interfacing the SCC/ESCC
X
X
X
X
X
X
X
X
X
X
3
0
0
0
0
0
0
1
0
0
0
X
X
X
X
X
X
X
X
X
1
2
0
1
0
0
0
0
0
1
0
0
X
X
X
X
X
X
X
X
X
X
1
0
0
0
0
0
0
0
1
0
0
0
X
X
X
X
X
X
X
X
X
X
0
X
0
0
0
0
0
0
0
0
2-9
2