Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 239

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

Application Note
Serial Communication Controller (SCC
Notes on Figure 6:
1. The master SCC sends EOP by switching from flag on
2. At initialization, all Slave stations were set up for SDLC
3. On receiving the EOP, the slave generates an
4. Note that there is a one bit time delay between
CMOS SCC AND ESCC
The discussion above applies to the NMOS SCC and the
CMOS SCC without the SDLC Frame Status FIFO feature.
The CMOS version and the ESCC have a SDLC Frame
Status FIFO for easier handling of the SDLC mode of
operation. The SDLC Status FIFO is designed for DMA
controlled SDLC receive for high speed SDLC data
transmission, or for systems whose CPU interrupt
processing is not fast.
This FIFO is able to store up to 10 packets’ worth of byte
count
(Overrun/Parity/CRC error status). To use this feature,
simply enable this FIFO and let DMA transfer data to
memory. While DMA is transferring received data to the
memory, the CPU will check the FIFO and locate the data
in memory, as well as the status information of the
received packet.
Other ESCC enhancements make it easier to handle the
SDLC mode of operation. These include:
CONCLUSION
This application note describes the basic operation of the
SCC in SDLC operational modes. With minor variations,
6-104
THE SDLC LOOP MODE (Continued)
idle to mark on idle
loop mode At this point, the Slave station connects its
RxD pin to TxD pin with gate propagation delay, and
starts to monitor Rx data for the EOP sequence.
External/Status Interrupt with Break/Abort bit set. A
one bit time delay is inserted between RxD and TxD.
(The GAOP,Go active on Poll, bit should be reset at
this point to avoid unexpected loop entry by the Slave
transmitter.) The Slave’s on-loop bit is set and the
receiver is in hunt mode.
received data and transmitted data.
(14-bit
count)
and
status
™
): SDLC Mode of Operation
information
5. When the Slave wants to transmit it must first receive
6. On receiving an EOP, the Slave interrupts with
7. Note that the flags overlap.
8. When the slave has sent all of its data the GAOP flag
9. When the closing flag has been sent the Slave reverts
10. The master must keep its output marking until its
For more details on these functions, please refer to the
SCC/ESCC Technical manual and related documents.
most of these operations also apply to the CMOS SCC
with Status FIFO enabled and the ESCC.
an EOP and have GAOP set.
Break/Abort clear. The EOP is converted to a flag, the
loop sending bit is set, and the transmitter will send
flags until data is written into the Transmit Buffer.
should be cleared so that the CRC is sent on
underrun.
to a one bit delay, which produces another EOP.
receiver has received all frames sent by secondaries.
Deeper FIFO (4 Bytes Transmit, and 8 Bytes receive)
Automatic Opening Flag transmission
Automatic EOM reset
Automatic /RTS deactivation
Fast /DTR//REQ mode
Complete CRC reception
Receive FIFO Antilock feature
Programmable DMA and interrupt request level
Improved data setup time specification
UM010901-0601