Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 219

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

Application Note
SCC in Binary Synchronous Communications
The Z8002 CPU must be operated in System mode in
order to execute privileged I/O instructions, so the Flag
Control
System/Normal (S//N), and the Vectored Interrupt Enable
(VIE) bits set. The Program Status Area Pointer (PSAP) is
loaded with address %4400 using the Load Control
instruction (LDCTL). If the Z8000 Development Module is
intended to be used, the PSAP need not be loaded by the
programmer as the development modules monitor loads it
automatically after the NMI button is pressed.
Register
WR9
WR4
WR10
WR6
WR7
WR2
WR11
WR12
WR13
WR14
WR15
WR5
WR3
WR1
WR9
6-84
INITIALIZATION (Continued)
Table 2. Programming Sequence for Initialization
Word
Value
(hex)
(FCW)
CD
AB
CE
C0
C1
10
20
16
03
00
64
08
09
0
0
Effect
Hardware reset
x1 clock, 16-bit sync,
sync mode enable
NRZ, CRC preset to zero
Any sync character “AB”
Any sync character “CD”
Interrupt vector “20”
Tx clock from BRG output,
TRxC pin = BRG out
Lower byte of time constant =
“CE” for 9600 baud
Upper byte = 0
BRG source bit = 1 for PCLK
as input, BRG enable
External interrupt disable
Tx 8 bits/character, CRC-16
Rx8 bits/character, Rx enable
(Automatic Hunt mode)
RxInt on 1st char & sp. cond.,
ext. int. disable)
MIE, VIS, Status Low
should
be
loaded
with
Since VIS and Status Low are selected in WR9, the
vectors listed in Table 3 will be returned during the
Interrupt Acknowledge cycle. Of the four interrupts listed,
only two, Ch A Receive Character Available and Ch A
Special Receive Condition, are used in the example given
here.
Vector
(hex)
28
2A
2C
2E
* “PS Address” refers to the location in the Program Status
Area where the service routine address is stored for that
particular interrupt, assuming that PSAP has been set to
4400 hex.
PS
Address*
(hex)
446E
4472
4476
447A
Table 3. Interrupt Vectors
Interrupt
Ch A Transmit Buffer Empty
Ch A External Status Change
Ch A Receive Char. Available
Ch A Special Receive Condition
UM010901-0601