Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 275

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

Application Note
Technical Considerations When Implementing LocalTalk Link Access Protocol
00000244
00000244 f5
00000245 c5
00000246 e5
00000247 f3
00000248 3e03
0000024a d3e8
0000024c 3ecc
0000024e d3e8
00000250 3e0a
00000252 d3e8
00000254 3ee0
00000256 d3e8
00000258 3e05
0000025a d3e8
0000025c 3e68
0000025e d3e8
00000260 3e05
00000262 d3e8
00000264 3e6a
00000266 d3e8
00000268 00
00000269 00
0000026a 3e05
0000026c d3e8
0000026e 3e68
00000270 d3e8
00000272 3e80
00000274 d3e8
00000276 0601
00000278
00000278 10fe
0000027a 3e05
6-140
600
601
602
603 txenq:
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653 csloop:
654
655
656
657
658
659
push
push
push
di
ld
out
ld
out
ld
out
ld
out
ld
out
ld
out
ld
out
ld
out
ld
out
ld
out
ld
out
ld
djnz
ld
LISTING 2
af
bc
hl
a,03h
(scc_cont),a
a,0cch
(scc_cont),a
a,0ah
(scc_cont),a
a,11100000b
(scc_cont),a
a,05h
(scc_cont),a
a,01101000b
(scc_cont),a
a,05h
(scc_cont),a
a,01101010b
(scc_cont),a
nop
nop
a,05h
(scc_cont),a
a,01101000b
(scc_cont),a
a,10000000b
(scc_cont),a
b,01h
csloop
a,05h
;*************************************************
;Subroutine to transmit the llapenq packet
;*************************************************
;save status and a reg
;save
;save
;
;make sure that
;no interrupt routine
;nor should interrupt
;occur during
;this subroutine.
;WR3
;8b/char,rx crc
;enable,addrs src
;and rx disabled
;select WR10
;idle with flags
;****enable transmitter *****
;select WR5
;enable tx
;
;
;****enable rs-422 driver *****
;select WR5
;enable tx,
;reset rts
;nop’s needed to complete 4.3 usec
;for 1 bit time enable of transmitter.
;total delay=2*(7+11+4) T states at 10 MHZ
;
;****disable rs-422 driver for 2 bit times*****
;select WR5
;enable tx, set rts
;
;reset txcrc
;delay count
;loop needed
;to complete
;8.6 usec min.
;or 2 bit times.
;****enable rs-422 driver for llap transmission*****
;select WR5
UM010901-0601