MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 1073
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MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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18.3.5.2.2
In RC mode, the PEXIWBAR[1–3] registers reside outside of the type 1 header; PEXIWBAR0 is the only
inbound BAR that resides in the Type 1 header (at offset 0x10).
If the transaction hits any window, the translation is performed and then the transaction is sent to memory.
If there is no hit to any one of the BARs, then a UR completion will be returned for non-posted
transactions. All posted transactions with no BAR hit are ignored.
Figure 18-19
18.3.5.2.3
The PCI Express inbound translation address registers, shown in
internal platform address to be used. Note that PEXITAR0 does not exist in the memory-mapped space; it
is a fixed 1-Mbyte translation to the internal configuration (CCSRBAR) space.
Freescale Semiconductor
Offset Window 1: 0xDE0
Reset
W
R
Window 2: 0xDC0
Window 3: 0xDA0
0
To Memory
shows the inbound transaction flow in RC mode.
Figure 18-20. PCI Express Inbound Translation Address Registers (PEXITAR n )
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
RC Inbound ATMU Implementation
PCI Express Inbound Translation Address Registers (PEXITAR n )
—
Inbound ATMUs
7
Figure 18-19. RC Inbound Transaction Flow
8
TEA
11 12
Memory or IO Base
Memory or IO Limit
Memory Base
Primary Side
Memory Limit
Prefetchable
Prefetchable
All zeros
Figure
18-20, contain the translated
TA
PCI Express Interface Controller
Secondary Side
Access: Read/Write
18-25
31
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