MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 1238
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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Debug Features and Watchpoint Facility
Table 21-11
The following table,
different interfaces supported by the watchpoint monitor.
21-14
13–15 Reserved
20–24 Reserved
26–31 Reserved
Bit
16
17
18
19
25
10
11
12
0–31
Bits
0
1
2
3
4
5
6
7
8
9
Write with local processor snoop
Write with no local processor snoop
Write with allocate(L2 stashing)
Write with allocate and lock (L2 stashing with locking) Write with allocate and lock
Reserved
Reserved
Reserved
Reserved
Read with local processor snoop
Read with no local processor snoop
Read with unlock
Reserved
Reserved
ATOMIC clear
ATOMIC set
ATOMIC decrement
ATOMIC increment
Address only transaction
WMTM Watchpoint monitor transaction mask. Each bit corresponds to a transaction type as defined in
Name
describes the WMTMR fields.
e500 Coherency Module Dispatch
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The transaction associated with any particular bit may be different depending on the interface being
monitored. A value of 1 for a given mask bit enables the matching of the transaction associated with that
bit. These bits are meaningful only when WMCR0[TMD]=0.
Table
21-12, defines the transactions associated with each transaction mask bit for the
Table 21-12. Transaction Types by Interface
Table 21-11. WMTMR Field Descriptions
Description
ATOMIC decrement
ATOMIC increment
Write with allocate
Description
Read with unlock
DDR Controller
ATOMIC clear
ATOMIC set
Write
Read
—
—
—
—
—
—
—
—
—
—
—
—
PCI Outbound
Memory Read
Memory write
I/O Read
Request
I/O write
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Non-posted Write
Read Response
PCI Express
Posted Write
Transaction
Outbound
Table
Read
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21-12.
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