MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 965

• Manufacturer Part Number: MPC8533EVTANG
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTANG

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 800MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

16.4.1.2.3
In extended chaining mode, the software must first build list and link descriptor segments in memory. Then
CLSDARn and ECLSDARn must be initialized to point to the first list descriptor in memory. The DMA
controller loads list descriptors and link descriptors from memory prior to a DMA transfer. The DMA
controller begins the transfer according to the link descriptor information loaded. Once the current link
descriptor is finished, the DMA controller reads the next link descriptor from memory and begins another
DMA transfer. If the current link descriptor is the last in the list, the DMA controller reads the next list
descriptor in memory. The transfer is finished if the current link descriptor is the last one in the last list in
memory or if an error condition occurs. The sequence of events to start and complete a transfer in extended
chaining mode is as follows:
16.4.1.2.4
In the extended mode, the single-write start feature allows a chain to be started by writing the current list
descriptor pointer. Setting MRn[CDSM/SWSM] causes MRn[CS] to be set automatically when
CLSDARn is written. (Note that ECLSDARn must be written first so that the full 36-bit descriptor address
is present when the chain starts.) The sequence of events to start and complete an extended chain using
single-write start mode is as follows:
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1. Build link and list descriptor segments in memory.
2. Poll the channel state (see
3. Initialize CLSDARn and ECLSDARn to point to the first list descriptor in memory.
4. Clear the mode register channel transfer mode bit, MRn[CTM], to indicate chaining mode.
5. Clear, then set the mode register channel start bit, MRn[CS], to start the DMA transfer.
6. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
7. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the last
1. Set MRn[CDSM/SWSM], MRn[CTM], and MRn[XFE] to indicate extended chaining and
2. Build list and link descriptor segments in local memory.
3. Poll the channel state (see
4. Initialize the current list descriptor address register to point to the first list descriptor segment in
5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
6. SRn[CB] is automatically cleared by the DMA controller after finishing the transfer of the last
MRn[XFE] must be set to indicate extended DMA mode. Other control parameters may also be
initialized in the mode register.
descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if an error
occurs during any of the transfers.
single-write start mode. Also other control parameters may be initialized in the mode register.
memory. This write automatically causes the DMA controller to begin the list descriptor fetch and
set MRn[CS].
descriptor segment, or if the transfer is aborted (MRn[CA] transitions from a 0 to 1), or if an error
occurs during any of the transfers.
Extended Chaining Mode
Extended Chaining Single-Write Start Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table
Table
16-21), to confirm that the specific DMA channel is idle.
16-21), to confirm that the specific DMA channel is idle.
DMA Controller
16-29