MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 561

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MPC8533EVTANG

Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTANG

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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12.4.7.5
The KEU status register, shown in
outputs. Writing to this location results in an address error being reflected in the KEU interrupt status
register.
Table 12-46
Freescale Semiconductor
Bits
40–47
48–55
56–57
Address KEU 0x3_E028
0–39
62
63
Bits
58
Reset
W
R
Name
Name
SR
HALT Indicates when the KEU core has halted due to an error.
MI
OFL
0
IFL
describes the KEU status register fields.
KEU Status Register (KEUSR)
Module initialization is nearly the same as software reset, except that the interrupt control register remains
unchanged. This module initialization includes execution of an initialization routine, completion of which is
indicated by the RESET_DONE bit in the KEU status register
0 Don’t reset
1 Reset most of KEU
Software reset.
Functionally equivalent to hardware reset (the RESET signal), but only for KEU. All registers and internal state
are returned to their defined reset state. Upon negation of the SR bit, the KEU enters a routine to perform proper
initialization of the parameter memories. The RD (reset done) bit in the KEU status register indicates when this
initialization is complete
0 Normal operation
1 Full KEU reset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Output FIFO level. The number of dwords currently in the output FIFO
Input FIFO level. The number of dwords currently in the input FIFO
Reserved
0 KEU not halted
1 KEU core halted (must be reset/re-initialized)
Note: Because the error causing the KEU to stop operating may be masked to the interrupt status register, the
Table 12-45. KEU Reset Control Register Field Descriptions (continued)
status register is used to provide a second source of information regarding errors preventing normal
operation.
Table 12-46. KEU Status Register Field Descriptions
Figure
Figure 12-61. KEU Status Register
39 40
12-61, is a read-only register that reflects the state of six status
OFL
All zeros
Description
Description
47 48
IFL
55 56 57
Security Engine (SEC) 2.1
HALT ICCR IE ID RD
58
Access: Read-only
59 60 61 62 63
12-83

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