MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 924
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MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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Enhanced Three-Speed Ethernet Controllers
Table 15-158
Table 15-159
15-194
Set up the MII Mgmt for a write cycle to external the PHY AN Advertisement register (write the PHY address and
eTSEC Signals
Set source clock divide by 14, for example, to insure that EC_MDC clock speed is not greater than 2.5 MHz.
The AN Advertisement register is at offset address 0x04 from the external PHY address. (in this case 0x11)
GTX_CLK125
MDIO
MDC
describes the shared signals for the RGMII interface.
describes the register initializations required to configure the eTSEC in RGMII mode.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Sum
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I/O
I/O
Table 15-159. RGMII Mode Register Initialization Steps
O
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
I
(This example has RGMII 10Mbps mode, Statistics Enable = 1)
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0100]
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
Signals
No. of
This indicates that the eTSEC MII Mgmt bus is idle.
1
1
1
Table 15-158. Shared RGMII Signals
Assign a Physical address to the TBI,
Setup the MII Mgmt clock speed,
to 02608C:876543, for example.
to 02608C:876543, for example.
Initialize MAC Station Address,
Initialize MAC Station Address,
(I/F Mode = 2, Full Duplex = 1)
GTX_CLK125
GMII Signals
set to 16, for example.
Initialize MACCFG2,
MDIO
MDC
Initialize ECNTRL,
Register address),
Clear Soft_Reset,
Set Soft_Reset,
Sum
I/O
I/O
O
I
Signals
No. of
1
1
1
Management interface clock
Management interface I/O
Reference clock
Function
Freescale Semiconductor
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