MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 598

• Manufacturer Part Number: MPC8533EVTANG
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTANG

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 800MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DUART
13.3
Table 13-3
the complete description of each register. Note that the full register address is comprised of CCSRBAR
together with the block base address and offset listed in
There are two complete sets of DUART registers (one for UART0 and one for UART1). The two UARTs
on the device are identical, except that the registers for UART0 are located at offset 0x4500 (local), and
the registers for UART1 are located at offset 0x4600 (local). Throughout this chapter, the registers are
described by a singular acronym: for example, LCR represents the line control register for either UART0
or UART1.
The registers in each UART interface are used for configuration, control, and status. The divisor latch
access bit, ULCR[DLAB], is used to access the divisor latch least- and most-significant bit registers and
the alternate function register. Refer to
more information on ULCR[DLAB].
All the DUART registers are one byte wide. Reads and writes to these registers must be byte-wide
operations.
detailed information about each register. Undefined byte address spaces within offset 0x000–0xFFF are
reserved.
In this table and in the register figures and field descriptions, the following access definitions apply:
13-4
UART_RTS[0:1]
•
•
•
•
•
Signal
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Memory Map/Register Definition
lists the DUART registers and their offsets. It lists the address, name, and a cross-reference to
Table 13-3
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O
Table 13-2. DUART Signals—Detailed Signal Descriptions (continued)
Request to send. UART_RTSx are active-low output signals that can be programmed to be
automatically negated and asserted by either the receiver or transmitter. When connected to the
clear-to-send (CTS) input of a transmitter, this signal can be used to control serial data flow.
Meaning
provides a register summary with references to the section and page that contains
Timing Assertion/Negation—Updated and driven at the rising edge of every CCB clock.
State
Asserted/Negated—Represents the data being transmitted on the respective UART
interface.
Section 13.3.1.7, “Line Control Registers (ULCR0, ULCR1),”
Table
Description
13-3.
Freescale Semiconductor
for