MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 152
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MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8533EVTANG
Manufacturer:
FREESCAL
Quantity:
513
Company:
Part Number:
MPC8533EVTANG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8533EVTANGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MPC8533VTALF PDF datasheet
- MPC8533VTALF PDF datasheet #2
- MPC8533VTALF PDF datasheet #3
- MPC8533VTALF PDF datasheet #4
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- Download datasheet (18Mb)
Signal Descriptions
3-12
LSSD_MODE
PCI_AD[31:0]
LSYNC_OUT
MSRCID[2:4]
LSYNC_IN
MCKE[0:3]
MDQ[0:63]
MDQS[0:7]
MDQS[0:8]
MECC[0:7]
MODT[0:3]
MCK[0:5],
MDIC[0:1]
MSRCID0
MSRCID1
LWE[1:3]/
MDM[0:7]
MCK[0:5]
MCS[0:3]
MBA[2:0]
MA[15:0]
LBS[1:3]
MDQS8
MDVAL
MCAS
MDM8
MRAS
Name
/LBS0
LWE0
MWE
MCP
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
LSSD mode
Local bus DLL
synchronization
Local bus DLL
synchronization
Local bus write enable
/byte select 1–3
Local bus write enable
/byte select 0
DDR address
DDR bank select
DDR column address strobe
DDR differential clocks (3
pairs/DIMM)
DDR clock enable
Machine check processor
DDR chip select (2/DIMM)
Driver impedence calibration
DDR data mask
DDR ECC data mask
DDR data
DDR data strobe
DDR ECC data strobe
(complement)
DDR ECC data strobe
Memory debug data valid
DDR error correcting code
DRAM On-Die Termination
DDR row address strobe
Memory debug source port
ID 2–4
Memory debug source port
ID 0
Memory debug source port
ID 1
DDR write enable
PCI address/data
Description
Table 3-2. Alphabetical Signal Reference (continued)
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
Functional
Debug/
Debug
Debug
Debug
Debug
Block
LBC
LBC
LBC
LBC
Test
PIC
PCI
Alternate Function(s)
cfg_host_agt[0:2]
cfg_mem_debug
cfg_ddr_debug
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Signals
No. of
16
12
64
32
1
1
1
3
1
3
1
4
1
4
2
8
1
8
9
1
1
8
4
1
3
1
1
1
Freescale Semiconductor
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
21-5/21-8
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
10-5/10-8
21-3/21-6
21-3/21-6
21-3/21-6
17-2/17-6
21-3/21-6
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
Table/
Page
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