MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 359

no-image

MPC8533EVTANG

Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTANG

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8533EVTANG
Manufacturer:
FREESCAL
Quantity:
513
Part Number:
MPC8533EVTANG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8533EVTANGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Table 9-32
9.4.1.27
The memory error interrupt enable register, shown in
select error interrupts. When an enabled interrupt condition occurs, the internal int signal is asserted to the
programmable interrupt controller (PIC).
Freescale Semiconductor
Offset 0xE48
Reset
25–27
0–23
Bits
24
28
29
30
31
W
R
0
MBED Multiple-bit ECC error disable
MSED Memory select error disable
Name
ACED Automatic calibration error disable
SBED Single-bit ECC error disable
describes the ERR_DISABLE fields.
Memory Error Interrupt Enable (ERR_INT_EN)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
0 Automatic calibration errors are enabled.
1 Automatic calibration errors are disabled.
Reserved
0 Multiple-bit ECC errors are detected if DDR_SDRAM_CFG[ECC_EN] is set. They are reported if
1 Multiple-bit ECC errors are not detected or reported.
0 Single-bit ECC errors are enabled.
1 Single-bit ECC errors are disabled.
Reserved
0 Memory select errors are enabled.
1 Memory select errors are disabled.
ERR_INT_EN[MBEE] is set. Note that uncorrectable read errors cause the assertion of core_fault_in ,
which causes the core to generate a machine check interrupt, unless it is disabled (by clearing
HID1[RFXE]). If RFXE is zero and this error occurs, MBED and ERR_INT_EN[MBEE] must be zero and
ECC_EN must be one to ensure that an interrupt is generated.
Figure 9-28. Memory Error Interrupt Enable Register (ERR_INT_EN)
Table 9-32. ERR_DISABLE Field Descriptions
All zeros
Figure
Description
9-28, enables ECC interrupts or memory
23
ACEE
24
25
27
MBEE SBEE — MSEE
28
DDR Memory Controller
Access: Read/Write
29
30
31
9-37

Related parts for MPC8533EVTANG