MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 1148
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MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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PCI Express Interface Controller
Figure 18-126
Figure 18-127
invariance.
Figure 18-128
Note that in all of these examples, the original addresses of the individual bytes within the scalars (as
created by the source) have been preserved.
18.4.1.2.1
All internal memory-mapped registers in the CCSR space use big endian byte ordering. However, the PCI
Express specification defines PCI Express configuration registers as little endian. All accesses to the PCI
Express configuration port, PEX_CONFIG_DATA, including the those targeting the internal PCI Express
configuration registers, use the address invariance policy as shown in
must access PEX_CONFIG_DATA with little-endian formatted data—either by using the lwbrx/stwbrx
instructions or by manipulating the data before writing to and after reading from PEX_CONFIG_DATA.
18-100
Address lsbs
Significance
Byte lane
Data
Address lsbs
Address lsbs
Significance
Significance
Byte lane
Byte lane
Data
Data
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
shows an outbound transfer of an 8-byte scalar, 0x5455_1617_CDCE_2728, using address
shows data flowing the other way, from a little endian source to a big endian destination.
shows an inbound transfer of a 2-byte scalar, 0x5837, using address invariance.
Byte Order for Configuration Transactions
MSB
000
54
0
Figure 18-127. Address Invariant Byte Ordering—8 bytes Outbound
Figure 18-126. Address Invariant Byte Ordering—4 bytes Inbound
Figure 18-128. Address Invariant Byte Ordering—2 bytes Inbound
001
55
1
Big endian source bus
010
16
2
MSB
011
011
41
—
3
3
011
17
Little endian
Little endian
source bus
3
source bus
010
010
42
—
2
2
CD CE
100
4
MSB LSB
001
001
43
58
1
1
101
5
LSB
000
000
44
37
0
0
110
27
6
LSB
111
28
7
MSB
111
28
7
MSB
MSB LSB
000
000
44
37
0
0
destination bus
destination bus
Little endian destination bus
110
27
6
Big endian
Big endian
001
001
43
58
1
1
101
CE CD
5
Figure
010
010
42
—
2
2
100
4
LSB
011
011
41
—
3
3
18-129. Therefore, software
011
17
3
010
16
2
Freescale Semiconductor
001
55
1
LSB
000
54
0
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