MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 215

• Manufacturer Part Number: MPC8533EVTANG
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTANG

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 800MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MMU operations are described in the EREF.
5.13.6
Unlike the AIM version of the architecture, where little-endian mode is controlled on a system basis, the
embedded category allows control of byte ordering on a memory page basis. In addition, the little-endian
byte ordering used is true little endian.
5.14
Table 5-8
Freescale Semiconductor
Cache protocol
Multiprocessor
functionality
Nexus support
R1 and R2 data
bus parity
Dynamic bus
snooping
Supported
TCR[WRC]
SPE and
floating-point
categories
HID0
implementation
Feature
Table 5-8. Differences Between the e500 Core and the PowerQUICC III Core Implementation
summarizes details of the PowerQUICC III-specific implementation of the e500 core.
PowerQUICC III Implementation Details
Little-Endian Mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The L2 cache is a write-through cache and does not support MESI cache protocol.
Because PowerQUICC III is designed for a uniprocessor environment, the following e500 functionality is not
implemented:
Nexus is not supported. The Nexus processor ID register (NPIDR) and the Nexus bus enable bit
(HID1[NEXEN]) are not supported.
R1 and R2 data bus parity are disabled on PowerQUICC III devices. HID1[R1DPE,R2DPE] are reserved.
The PowerQUICC III devices do not perform dynamic bus snooping as described here. That is, when the e500
core is in core-stopped state (which is the state of the core when the PowerQUICC III device is in either the
nap or sleep state), the core is not awakened to perform snoops on global transactions. Therefore, before
entering nap or sleep modes, L1 caches should be flushed if coherency is required during these power-down
modes. For more information, see
PowerQUICC III devices define values for 00, 01, 10, and 11, as described in
The SPE (which includes the embedded vector and scalar floating-point instructions) will not be implemented
in the next generation of PowerQUICC devices. Freescale Semiconductor strongly recommends that use of
these instructions be confined to libraries and device drivers. Customer software that uses these instructions
at the assembly level or that uses SPE or floating-point intrinsics will require rewriting for upward compatibility
with next generation PowerQUICC devices.
The e500v2 core implements SPE double-precision floating-point instructions.
Freescale Semiconductor offers a libcfsl_e500 library that uses SPE instructions. Freescale Semiconductor
will also provide future libraries to support next generation PowerQUICC devices.
SEL_TBCLK bit. Selects time base clock. If this bit is set and the time base is enabled, the time base is based
on the TBCLK input, which on the PowerQUICC III devices is RTC.
• The memory coherence bit, M, which is controlled through MAS2[M] and MAS4[MD] has no effect.
• HID1[ABE] has meaning only in that it must be set to ensure that cache and TLB management instructions
• Dynamic snooping does not occur in power-stopped state (see the note below in the entry for dynamic bus
operate properly with respect to the L2 cache.
snooping).
Section 19.5.1.9, “Snooping in Power-Down Modes.”
PowerQUICC III Implementation
Table 6-9 on page
Core Complex Overview
6-15.
5-31