MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 323

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MPC8533EVTANG

Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTANG

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Chapter 9
DDR Memory Controller
9.1
The fully programmable DDR SDRAM controller supports most JEDEC standard x8, x16, or x32 DDR2
and DDR memories available. In addition, unbuffered and registered DIMMs are supported. However,
mixing different memory types or unbuffered and registered DIMMs in the same system is not supported.
Built-in error checking and correction (ECC) ensures very low bit-error rates for reliable high-frequency
operation. Dynamic power management and auto-precharge modes simplify memory system design. A
large set of special features, including ECC error injection, support rapid system debug.
Figure 9-1
Section 9.5, “Functional Description,”
Freescale Semiconductor
Introduction
is a high-level block diagram of the DDR memory controller with its associated interfaces.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
In this chapter, the word ‘bank’ refers to a physical bank specified by a chip
select; ‘logical bank’ refers to one of the four or eight sub-banks in each
SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank address
(MBA) pins during a memory access.
contains detailed figures of the controller.
NOTE
9-1

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