MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 666
MPC8533EVTANG
Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTANG
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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Local Bus Controller
14.4.3.2
Following a system reset, initialization software must set up the programmable parameters in the memory
controller banks registers (ORn, BRn, LSDMR). After all memory parameters are configured, system
software should execute the following initialization sequence for each SDRAM device.
The initial commands are executed by setting LSDMR[OP] and accessing the SDRAM with any write that
hits the relevant bank. Since the result of any update to the LSDMR must be in effect before accessing the
SDRAM with any write, a write to LSDMR should be followed immediately by a read from LSDMR,
which must complete prior to an initial write to SDRAM. Further, the first write to SDRAM should be
followed immediately by an SDRAM read, which must complete prior to additional LSDMR updates. This
enforces a proper ordering between updates to the LSDMR and write accesses to the SDRAM. If the
initialization is being done by the e500, this described protocol is guaranteed only if the SDRAM is
mapped as cache-inhibited and guarded, as the CCSR memory region containing LSDMR should be. If the
initialization is from an external host, said host must ensure completion of LSDMR and SDRAM reads
prior to subsequent writes, as described above.
Note that software should ensure that no memory operations begin until this process completes.
14-48
•
•
•
Issue a PRECHARGE-ALL-BANKS command
Issue eight AUTO-REFRESH commands
Issue a MODE-SET command to initialize the mode register
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SDRAM Power-On Initialization
Local Bus
Controller
Figure 14-34. Connection to a 32-Bit SDRAM with 12 Address Lines
LSDDQM[0:3]
LAD[0:31]
LA[27:29]
LSDRAS
LSDCAS
LSDA10
LSDWE
LCLK
LCKE
LCS1
LALE
LAD[18,20:26]
Memory Address
Memory Data
A[11,9:3]
WE
RAS
CAS
CS
DQM[3:0]
A10
A[2:0]
DQ[31:0]
CLK
CKE
32-Bit Port Size
SDRAM
Freescale Semiconductor
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