IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 101

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

3.25
to High-Z;
ers will be High-Z (no clock means this: the input on the OSCI pin is in
high/low level, or the duty cycle is less than 30% or larger than 70%);
Drivers will be High-Z;
to High-Z;
the transmit clock is from the recovered clock from the line side. When
the recovered clock from the line side is lost, the Line Driver in the corre-
sponding link will be High-Z;
the transmit clock is from the backplane timing clock. When the back-
plane timing clock is lost (i.e., no transition for more than 72 T1/E1/J1
cycles), the Line Driver in the corresponding link will be High-Z. How-
ever, there is an exception in this case. That is, if the link is in Remote
Loopback mode, the Line Driver will not be High-Z.
responding link will be High-Z.
impedance state immediately.
tection can be enabled. The driver’s output current (peak to peak) is lim-
ited to 110 mA typically. When the output current exceeds the limitation,
the transmit driver failure will be captured by the DF_S bit. Selected by
the DF_IES bit, a transition from ‘0’ to ‘1’ on the DF_S bit or any transi-
tion from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the DF_S bit will set the DF_IS bit.
When the DF_IS bit is ‘1’, an interrupt on the INT pin will be reported if
enabled by the DF_IE bit.
IDT82P2282
The Line Driver can be set to High-Z for redundant application.
The following ways will set the drivers to High-Z:
1. Setting the THZ pin to high will globally set both the Line Drivers
2. When there is no clock input on the OSCI pin, both the Line Driv-
3. After software reset, hardware reset or power on, both the Line
4. Setting the T_HZ bit to ‘1’ will set the corresponding Line Driver
5. In Transmit Clock Master mode, if the XTS bit is ‘1’, the source of
6. In Transmit Clock Slave mode, if the XTS bit is ‘0’, the source of
7. When the transmit path is power down, the Line Driver in the cor-
By these ways, the TTIPn and TRINGn pins will enter into high
Controlled by the DFM_ON bit, the output driver short-circuit pro-
LINE DRIVER
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DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
August 20, 2009