IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 174

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

T1/J1 Mode (062H, 162H)
FDLBYP:
code (‘FFFF’ for T1 / ‘FF7E’ for J1).
(b2~0, T1/J1-066H,... & b7~0, T1/J1-065H,...), the M[3:1] bits (b5~3, T1/J1-066H,...), the A[2:1] bits (b1~0, T1/J1-067H,...) and the S[4:1] bits (b5~2,
T1/J1-067H,...) respectively.
CRCBYP:
the current ESF frame.
FDIS:
Programming Information
IDT82P2282
Bit Name
Default
Bit No.
Type
In ESF format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: Enable the DL bit position to be replaced by the Bit-Oriented Code, the Automatic Performance Report Message, the HDLC data or the idle
= 1: Disable the DL bit position to be replaced by the above codes.
In T1 DM format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: The ‘D’ bit in Bit 6 of each Channel 24 is replaced with the HDLC data.
= 1: Disable the D bit position to be replaced by the HDLC data.
In SLC-96 format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: The Concentrator (C) bit, the Maintenance (M) bit, the Alarm (A) bit and the Switch (S) bit are replaced by the contents in the C[11:1] bits
= 1: Disable the Concentrator (C) bit, the Maintenance (M) bit, the Alarm (A) bit and the Switch (S) bit replacement.
This bit is valid in ESF format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’.
= 0: The calculated 6-bit CRC of the previous ESF frame is inserted in the current CRC-bit positions in every 4th frame starting with Frame 2 of
= 1: Disable the CRC-6 insertion.
= 0: Enable the generation of the SF / ESF / T1 DM / SLC-96 frame.
= 1: Disable the generation of the SF / ESF / T1 DM / SLC-96 frame.
7
6
Reserved
5
4
174
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3
FDLBYP
R/W
2
0
CRCBYP
R/W
1
0
August 20, 2009
FDIS
R/W
0
0