IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 197

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

RRST:
096H,... / 097H,...) and the EMP bit (b1, T1/J1-095H,... / 096H,... / 097H,...).
T1/J1 RHDLC1 RFIFO Access Status (095H, 195H)
T1/J1 RHDLC2 RFIFO Access Status (096H, 196H)
T1/J1 RHDLC3 RFIFO Access Status (097H, 197H)
EMP:
PACK:
Programming Information
IDT82P2282
Bit Name
Bit Name
Bit Name
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
A transition from ‘0’ to ‘1’ on this bit resets the corresponding HDLC Receiver. The reset will clear the FIFO, the PACK bit (b0, T1/J1-095H,... /
The function of the above three sets of registers are the same. However, they correspond to different RHDLC.
= 0: The FIFO is not empty.
= 1: The FIFO is empty, i.e., all the blocks are read from the FIFO.
The corresponding HDLC Receiver reset will clear this bit.
= 0: The byte read from the FIFO is not an overhead byte.
= 1: The byte read from the FIFO is an overhead byte.
The corresponding HDLC Receiver reset will clear this bit.
7
7
7
6
6
6
5
5
5
Reserved
Reserved
Reserved
4
4
4
197
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3
3
3
2
2
2
EMP
EMP
EMP
R
R
R
1
1
1
1
1
1
August 20, 2009
PACK
PACK
PACK
R
R
R
0
0
0
0
0
0