IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 351

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

RPLC:
timeslot.
responds to one timeslot.
TS15 and TS17 to TS31 respectively. Each address corresponds to one timeslot.
E1 Timeslot Control Register (00H ~ 1FH)
SUBST[2:0]:
SINV, OINV, EINV:
Programming Information
IDT82P2282
SUBST[2:0]
Bit Name
the others
Default
Bit No.
Type
The indirect registers of RPLC addressed from 00H to 1FH are the Timeslot Control Registers for TS0 to TS31. Each address corresponds to one
The indirect registers of RPLC addressed from 20H to 3FH are the Data Trunk Conditioning Code Registers for TS0 to TS31. Each address cor-
The indirect registers of RPLC addressed from 41H to 4FH and from 51H to 5FH are the Signaling Trunk Conditioning Code Registers for TS1 to
When the GSUBST[2:0] bits (b2~0, E1-0D0H,...) are ‘000’, these bits select the replacement on a per-timeslot basis.
These three bits select how to invert the bits in the corresponding timeslot.
000
001
010
011
SINV
0
0
0
0
1
1
1
1
No operation.
The data of the corresponding timeslot is replaced by the data trunk code set in the DTRK[7:0] bits (b7~0, E1-ID-20~3FH).
The data of the corresponding timeslot is replaced by the A-Law digital milliwatt pattern.
The data of the corresponding timeslot is replaced by the µ-Law digital milliwatt pattern.
Reserved.
SUBST2
R/W
7
0
OINV
0
0
1
1
0
0
1
1
EINV
0
1
0
1
0
1
0
1
SUBST1
R/W
6
0
No inversion.
Invert the even bits (bit 2, 4, 6, 8) of the corresponding timeslot (bit 1 is the MSB).
Invert the odd bits (bit 3, 5, 7) except the MSB of the corresponding timeslot (bit 1 is the MSB).
Invert the bits from bit 2 to bit 8 of the corresponding timeslot (bit 1 is the MSB).
Invert the MSB (bit 1) of the corresponding timeslot.
Invert the MSB (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding timeslot.
Invert all the odd bits (bit 1, 3, 5, 7) of the corresponding timeslot (bit 1 is the MSB).
Invert all the bits (bit 1 ~ bit 8) of the corresponding timeslot (bit 1 is the MSB).
SUBST0
R/W
5
0
SINV
R/W
Replacement Selection
4
0
351
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Bit Inversion
OINV
R/W
3
0
EINV
R/W
2
0
G56K
R/W
1
0
August 20, 2009
GAP
R/W
0
0