IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 108

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

4
4.1
4.2
values.
power-up and the low signal should last at least 10 ms to initialize the
device. After the RESET pin is asserted high, all the registers are in their
default values and can be accessed after 2 ms (refer to Figure 37).
software anytime. When it is hardware reset, the RESET pin should be
asserted low for at least 100 ns. Then all the registers are in their default
values and can be accessed after 2 ms (refer to Figure 38). When it is
software reset, a write signal to the Software Reset register will reset all
the registers except the T1/J1 Or E1 Mode register to their default val-
ues. Then the registers are accessible after 2 ms. However, the T1/J1
Or E1 Mode register can not be reset by the software reset. It can only
be reset by the hardware reset.
the OSCI pin is available.
Mode register is changed, a software reset must be applied.
Operation
IDT82P2282
Microprocessor
To power on the device, the following sequence should be followed:
1. Apply ground;
2. Apply 3.3 V;
3. Apply 1.8 V.
When the device is powered-up, all the registers contain random
The hardware reset pin RESET must be asserted low during the
During normal operation, the device can be reset by hardware or
Hardware or software reset can only be applied when the clock on
It should be mentioned that when the setting in the T1/J1 Or E1
Figure 37. Hardware Reset When Powered-Up
Interface
RESET
OPERATION
Vdd
POWER-ON SEQUENCE
RESET
10ms
2ms
access
108
4.3
ting the R_OFF bit. During the receive path power down, the output of
the corresponding path is low.
by the T_OFF bit. During the transmit path power down, the output of the
corresponding path is High-Z.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Microprocessor
Figure 38. Hardware Reset In Normal Operation
The receive path of any of the two links can be power down by set-
The transmit path of any of the two links can be set to power down
Interface
RESET
RECEIVE / TRANSMIT PATH POWER DOWN
100 ns
2ms
August 20, 2009
access