IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 51

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

IDT82P2282
3.9.2
formance monitoring. For different framing format, the counters are used
differently. The overflow of each counter is reflected by an Overflow Indi-
cation Bit, and can trigger an interrupt if the corresponding Overflow
Interrupt Enable Bit is set. This is shown in Table 22.
indirect registers every one second automatically if the AUTOUPD bit is
‘1’;
Functional Description
Table 24: Monitored Events In E1 Mode
Bipolar Violation (BPV) Error (in AMI decoding) or HDB3 Code Violation (CV) Error (in HDB3 decoding)
FAS/NFAS Bit/Pattern Error
CRC-4 Error
Far End Block Error
The the new-found Basic frame alignment pattern position differs from the previous one
Out of Basic frame synchronization
PRGD Bit Error
NT FEBE Error
NT CRC Error
Several internal counters are used to count different events for per-
The internal counters can be updated in two ways:
1. Auto-Update: Content in the internal counters is transferred to
E1 MODE
Event
51
indirect registers when there is a transition from ‘0’ to ‘1’ on the UPDAT
bit, no matter whether the AUTOUPD bit is ‘1’ or ‘0’.
start a new round of counting. No error event is lost during the update.
ADDR[3:0] bits. The LINKSEL bit selects the link and the ADDR[3:0] bits
select the specific PMON indirect register. Data read from the indirect
register is held in the DAT[7:0] bits.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
2. Manual-Update: Content in the internal counters is transferred to
All the internal counters will be resetted after the update and will
The indirect registers are addressed by the LINKSEL and
PRGD[15:0]
TCRCE[9:0]
TFEBE[9:0]
CRCE[9:0]
COFA[2:0]
FEBE[9:0]
LCV[15:0]
FER[11:0]
OOF[4:0]
Counter
Overflow Interrupt
Indication Bit
TFEBEOVI
PRGDOVI
COFAOVI
TCRCOVI
FEBEOVI
CRCOVI
OOFOVI
FEROVI
LCVOVI
August 20, 2009
Overflow Interrupt
TFEBEOVE
PRGDOVE
Enable Bit
COFAOVE
TCRCOVE
FEBEOVE
OOFOVE
CRCOVE
LCVOVE
FEROVE