IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 303

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

E1 Error Insertion (06FH, 16FH)
CRCINV:
CRCPINV:
CASPINV:
NFASINV:
FASALLINV:
FAS1INV:
Programming Information
IDT82P2282
Bit Name
Default
Bit No.
Type
This bit is valid when the CRC Multi-frame or the Modified CRC Multi-frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert all 4 calculated CRC bits in one Sub-Multi-Frame.
This bit is cleared when the inversion is completed.
This bit is valid when the CRC Multi-frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one 6-bit CRC Multi-Frame alignment pattern (‘001011’).
This bit is cleared when the inversion is completed.
This bit is valid when the CAS Multi-frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one 4-bit Signaling Multi-Frame alignment pattern (‘0000’).
This bit is cleared when the inversion is completed.
This bit is valid when the Basic frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one NFAS bit (the Bit 2 of TS0 of each odd frame).
This bit is cleared when the inversion is completed.
This bit is valid when the Basic frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one 7-bit FAS pattern (the Bit 2 ~ Bit 8 of TS0 of each even frame).
This bit is cleared when the inversion is completed.
This bit is valid when the Basic frame is generated.
A transition from ‘0’ to ‘1’ on this bit will invert one FAS bit (the Bit 2 ~ Bit 8 of TS0 of each even frame).
This bit is cleared when the inversion is completed.
7
Reserved
6
CRCINV
R/W
5
0
CRCPINV
R/W
4
0
303
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
CASPINV
R/W
3
0
NFASINV
R/W
2
0
FASALLINV
R/W
1
0
August 20, 2009
FAS1INV
R/W
0
0