IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 73

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

3.18
the device. The data input to the two links can be aligned with each
other or input independently. The timing clocks and framing pulses can
be provided by the system backplane or obtained from the processed
data of each link. The Transmit System Interface supports various con-
figurations to meet various requirements in different applications.
3.18.1
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the TSDn pin is used to input the data to each link at the bit rate of 1.544
Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed
Mode, the data is byte-interleaved from one high speed data stream and
inputs on the MTSD pin at the bit rate of 8.192 Mb/s. The demultiplexed
data input to the two links is 2.048 Mb/s on the system side and con-
verted into 1.544 Mb/s format to the device.
Table 42: Operating Modes Selection In T1/J1 Transmit Path
3.18.1.1
signal on the TSCKn pin and framing pulse on the TSFSn pin to input
the data on each TSDn pin. The signaling bits on the TSIGn pin are per-
channel aligned with the data on the TSDn pin.
face is clocked by the TSCKn. The active edge of the TSCKn used to
update the pulse on the TSFSn is determined by the FE bit. The active
edge of the TSCKn used to sample the data on the TSDn and TSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the TSFSn is ahead.
F-bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFSn is selected by the FSINV bit.
IDT82P2282
NOTE:
1. When the G56K, GAP bits in TPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Transmit Multiplexed mode.
TMUX TMODE
0
1
The Transmit System Interface determines how to input the data to
In T1/J1 mode, the Transmit System Interface can be set in Non-
In the Transmit Clock Master mode, each link uses its own timing
In the Transmit Clock Master mode, the data on the system inter-
In the Transmit Clock Master mode, the TSFSn can indicate each
TRANSMIT SYSTEM INTERFACE
X
0
1
T1/J1 MODE
Transmit Clock Master Mode
G56K, GAP /
not all 0s
FBITGAP
00 / 0
X
X
1
MAP[1:0]
00
01
10
01
10
11
11
X
2
Transmit Clock Master Full T1/J1
Transmit Clock Master Fractional T1/J1
Transmit Clock Slave - T1/J1 Rate
Transmit Clock Slave - T1/J1 Mode E1 Rate per G.802
Transmit Clock Slave - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per G.802
Transmit Multiplexed - T1/J1 Mode E1 Rate per One Filler Every
Four CHs
Transmit Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
Operating Mode
73
TSFSn, however in Transmit Clock Slave mode, TSCKn & TSFSn are
input the device from outside.
the entire T1/J1 frame, the Transmit System Interface is in Transmit
Clock Master Full T1/J1 mode. If only the clocks aligned to the selected
channels are output on TSCKn, the Transmit System Interface is in
Transmit Clock Master Fractional T1/J1 mode.
equal to 1.544 Mb/s (i.e., the line data rate) or 2.048 Mb/s or 8.192 Mb/s.
If the backplane data rate is 2.048 Mb/s or 8.192 Mb/s, the Transmit
System Interface is in T1/J1 mode E1 rate and the data to be transmitted
will be mapped to 1.544 Mb/s i device per 3 kinds of schemes.
each link into various operating modes and the pins’ direction of the
transmit system interface in different operating modes.
mit Clock Master Full T1/J1 mode and Transmit Clock Master Fractional
T1/J1 mode.
3.18.1.1.1
Master mode, the special feature in this mode is that the TSCKn is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked in by the TSCKn.
3.18.1.1.2
Master mode, the special feature in this mode is that the TSCKn is a
gapped 1.544 MHz clock (no clock signal during the selected channel).
‘1’. The TSCKn is also gapped during the channels or the Bit 8 duration
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
In Transmit Clock Master mode, the device output TSCKn and
In the Transmit Clock Master mode, if TSCKn outputs pulses during
In the Transmit Clock Slave mode, the backplane data rate may be
Table 42 summarizes how to set the transmit system interface of
The Transmit Clock Master mode includes two sub-modes: Trans-
Besides all the common functions described in the Transmit Clock
Besides all the common functions described in the Transmit Clock
The TSCKn is gapped during the F-bit if the FBITGAP bit is set to
Transmit Clock Master Full T1/J1 Mode
Transmit Clock Master Fractional T1/J1 Mode
TSDn, TSIGn, TSCKn, TSFSn
MTSCK, MTSFS, MTSD,
Transmit System Interface Pin
TSDn, TSIGn
MTSIG
Input
August 20, 2009
TSCKn, TSFSn
Output
X
X