IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 253

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

E1 Receive Jitter Attenuation Configuration (027H, 127H)
RJITT_TEST:
rent interval between the read and write pointer of the FIFO will be written into the RJITT[6:0] bits (b6~0, E1-039H,...).
rent interval is compared with the old one in the RJITT[6:0] bits (b6~0, E1-039H,...) and the larger one will be indicated by the RJITT[6:0] bits (b6~0,
E1-039H,...); otherwise, the value in the RJITT[6:0] bits (b6~0, E1-039H,...) is not changed.
RJA_LIMT:
of the JA can be widened to track the short term input jitter, thereby avoiding data corruption. This bit selects whether the bandwidth is normal or wid-
ened.
bits window.
RJA_E:
RJA_DP[1:0]:
RJA_BW:
Programming Information
IDT82P2282
Bit Name
Default
Bit No.
= 0: The real time interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, E1-039H,...). That is, the cur-
= 1: The peak-peak interval between the read and write pointer of the FIFO is indicated in the RJITT[6:0] bits (b6~0, E1-039H,...). That is, the cur-
When the read and write pointer of the FIFO are within 2/3/4 bits (corresponding to the FIFO depth) of overflowing or underflowing, the bandwidth
= 0: Normal bandwidth is selected.
= 1: Widen bandwidth is selected. In this case, the JA will not attenuate the input jitter until the read/write pointer’s position is outside the 2/3/4
= 0: Disable the Receive Jitter Attenuator.
= 1: Enable the Receive Jitter Attenuator.
These two bits select the Jitter Attenuation Depth.
= 00: The Jitter Attenuation Depth is 128-bit.
= 01: The Jitter Attenuation Depth is 64-bit.
= 10 / 11: The Jitter Attenuation Depth is 32-bit.
This bit select the Jitter Transfer Function Bandwidth.
= 0: 6.77 Hz.
= 1: 0.87 Hz.
Type
7
Reserved
6
RJITT_TEST
R/W
5
0
RJA_LIMT
253
R/W
4
0
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
RJA_E
R/W
3
0
RJA_DP1
R/W
2
0
RJA_DP0
R/W
1
0
August 20, 2009
RJA_BW
R/W
0
0