IDT82P2282PF IDT, Integrated Device Technology Inc, IDT82P2282PF Datasheet - Page 170

• Manufacturer Part Number: IDT82P2282PF
• Description: TXRX T1/J1/E1 2CHAN 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2282PF

• Number Of Drivers/receivers: 2/2
• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82P2282PF

COFAI:
T1/J1 RDL0 (056H, 156H)
C[8:1]:
are updated every SLC-96 frame.
T1/J1 RDL1 (057H, 157H)
M[3:1]:
are updated every SLC-96 frame.
C[11:9]:
are updated every SLC-96 frame.
Programming Information
IDT82P2282
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
= 0: The F bit position is not changed.
= 1: The new-found F bit position differs from the previous one.
This bit will be cleared if a ’1’ is written to it.
In SLC-96 format, these bits together with the C[11:9] bits reflect the content in the Concentrator bits. The C[1] bit is the LSB.
In de-bounce condition, these bits are updated if the received Concentrator bits are the same for 2 consecutive SLC-96 frames; otherwise they
They are held during out of SLC-96 synchronization state.
In SLC-96 format, these bits reflect the content in the Maintenance bits. The M[1] bit is the LSB.
In de-bounce condition, these bits are updated if the received Maintenance bits are the same for 2 consecutive SLC-96 frames; otherwise they
They are held during out of SLC-96 synchronization state.
In SLC-96 format, these bits together with the C[8:1] bits reflect the content in the Concentrator bits. The C[11] bit is the MSB.
In de-bounce condition, these bits are updated if the received Concentrator bits are the same for 2 consecutive SLC-96 frames; otherwise they
They are held during out of SLC-96 synchronization state.
C8
R
7
0
7
Reserved
C7
R
6
0
6
M3
C6
R
R
5
0
5
0
M2
C5
R
R
4
0
4
0
170
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
M1
C4
R
R
3
0
3
0
C11
C3
R
R
2
0
2
0
C10
C2
R
R
1
0
1
0
August 20, 2009
C1
C9
R
R
0
0
0
0