ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 102

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
DDC INTERFACE (Cont’d)
DDC2B Mode: The DDC1/2B Interface enters
DDC2B mode either from the transition state or
from the initial state if software sets the HWPE bit
while P&D only or FPDI-2 mode is selected.
Once in DDC2B mode, the Interface always acts
as a slave following the protocol described in
Figure
The DDC1/2B Interface continuously monitors the
SDA and SCL lines for a START condition and will
Figure 62. DDC2B protocol (example)
102/144
SDA
SCL
62.
Start
Legend:
Device Slave
Address
A0h
Italics = data / control signal from display
Bold = data / control signal from host
Ack
Data Address
00h
Ack
Stop
Start A1h
Device Slave
Address
not respond (no acknowledge) until one is found.
A STOP condition at the end of a Read command
(after a NACK) forces the stand-by state. A STOP
condition at the end of a Write command triggers
the internal DMA write cycle.
The Interface samples the SDA line on the rising
edge of SCL and outputs data on the falling edge
of SCL. In any case SDA can only change when
SCL is low.
Ack
Data1
128 / 256 bytes EDID
Ack
DataN
Nack
Stop