ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 95

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

4.8 DDC INTERFACE (DDC)
4.8.1 Introduction
The DDC (Display Data Channel) Bus Interface is
mainly used by the monitor to identify itself to the
video controller, by the monitor manufacturer to
perform factory alignment, and by the user to
adjust the monitor’s parameters.
The DDC interface consists of two parts:
4.8.2 DDC Interface Features
4.8.2.1 Hardware DDC1/2B Interface Features
Figure 56. DDC Interface Overview
A
supporting
specification 3.0 compliant). It accesses the
ST7 on-chip memory directly through a built-in
DMA engine.
A second interface, supporting the slave I
functions for handling DDC/CI mode (DDC2Bi),
factory alignment or Enhanced DDC (EDDC) by
software.
Full
communications (VESA specification versions 2
and 3)
Hardware detection of DDC2B addresses A0h/
A1h and optionally A2h/A3h (P&D) or A6h/A7h
(FPDI-2)
Separate mapping of EDID version 1 (128
bytes) and EDID version 2 (256 bytes) when
both must coexist
Support for error recovery mechanism
Detection
conditions
fully
hardware
VSYNC
VSYNC2
SCL
SDA
hardware-implemented
of
DDC1
misplaced
support
VSYNCI2
VSYNCI
and
SDAD
SCLD
Start
DDC2B
for
and
DDC1/2B
interface,
(VESA
Stop
2
C
4.8.2.2 DDC/CI - Factory Interface Features
General I
I
2
C Slave Features:
– Parallel bus /I
– Interrupt generation
– Standard I
– 7-bit Addressing
– I
– Start bit detection flag
– Detection of misplaced Start or Stop condition
– Transfer problem detection
– Address Matched detection
– Programmable Address detection and/or
– End of byte transmission flag
– Transmitter/Receiver flag
– Stop condition Detection
I
DMA transfer from any memory location and to
RAM
Automatic memory address incrementation
End of data downloading flag and interrupt
capability
2
C byte, random and sequential read modes
Hardware detection of Enhanced DDC (ED-
DC) addresses (60h/61h)
2
C bus busy flag
2
C Features:
2
(DDC/CI - Factory Alignment)
C mode/Fast I
ST72774/ST727754/ST72734
2
HARDWARE DDC1/2B
C protocol converter
INTERFACE
INTERFACE
I2C SLAVE
2
C mode
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