ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 72

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

ST72774/ST727754/ST72734
SYNC PROCESSOR (SYNC) (Cont’d)
HORIZONTAL SYNC GENERATOR REGISTER
(HGENR)
Read/Write
Reset Value: 0000 0000 (00h)
Case HVGEN = 1: Generation mode
In this mode, this register contains the Hsync free-
running frequency.
The generated signal is:
Note: The value in HGENR must be in the range [8..255] .
Case HVGEN = 0: Analyzer/corrector Mode
Sub-case HACQ = 1: Analyzer Mode
By setting HACQ bit by software the Analyzer
mode starts. When HACQ is cleared by hardware,
HGENR returns the duration of HSYNCO/
HFBACK low level. The analysis should be done
before corrector mode.
Sub-case HACQ = 0: Corrector Mode
In this mode, the final HSYNCO signal on the pin
can be corrected in order to detect and inhibit pre/
post equalization pulses.
72/144
MSB
- Pulse width: 2 µs.
- Period PH = ((HGENR+1)/4) µs.
- Polarity: Positive
7
LSB
0
VERTICAL SYNC GENERATOR REGISTER
(VGENR)
Read/Write
Reset Value: 0000 0000 (00h)
Case HVGEN = 1: Generation mode
In this mode, this register contains the Vsync free-
running frequency (11-bit value).
The generated signal is:
Note: The value in VGENR must be in the range [5..255]
Case HVGEN = 0: Analyzer/Corrector Mode
Sub-case VACQ = 1: Analyzer Mode
Set the VACQ bit to start analyzer mode. When
VACQ is cleared by hardware, VGENR/CFGR
returns the number of scan lines during the
VSYNCO/VFBACK low level period.
Sub-case VACQ = 0: Corrector Mode
VSYNCO pulse width is extended by VGENR scan
lines. If VGENR = 0, all VSYNCO corrections are
disabled.
MSB
- Pulse width: 4 * PH µs (horizontal period).
- Period PV = PH * (V11bits) µs.
- Polarity: Positive
7
The Vsync generation mode works as an 11-bit hor-
izontal line counter (2047 scan lines per frame
max.). The 3 LSB are in the CFGR register. Refer
to
Figure
44.
LSB
0