ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 17

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

CPU REGISTERS (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
The Stack Pointer is a 16-bit register which is
always pointing to the next free location in the
stack. It is then decremented after data has been
pushed onto the stack and incremented before
data is popped from the stack (see
Since the stack is 256 bytes deep, the most
significant byte is forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer
instruction (RSP), the Stack Pointer contains its
reset value (the SP7 to SP0 bits are set) which is
the stack higher address.
Figure 6. Stack Manipulation Example
SP7
@ 0100h
@ 01FFh
15
0
7
SP
SP6
0
Subroutine
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
CALL
PCH
PCL
SP5
0
SP
SP4
0
SP3
Interrupt
0
event
PCH
PCH
PCL
PCL
CC
X
A
SP2
0
Figure
SP
SP1
0
6).
PUSH Y
SP0
PCH
PCH
PCL
PCL
8
1
0
CC
Y
A
X
SP
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD
instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit,
without
previously stored information is then overwritten
and therefore lost. The stack also wraps in case of
an underflow.
The stack is used to save the return address
during a subroutine call and the CPU context
during an interrupt. The user may also directly
manipulate the stack by means of the PUSH and
POP instructions. In the case of an interrupt, the
PCL is stored at the first location pointed to by the
SP. Then the other registers are stored in the next
locations as shown in
– When an interrupt is received, the SP is decre-
– On return from interrupt, the SP is incremented
A subroutine call occupies two locations and an
interrupt five locations in the stack area.
mented and the context is pushed on the stack.
and the context is popped from the stack.
POP Y
PCH
PCL
PCH
PCL
CC
indicating
A
X
ST72774/ST727754/ST72734
SP
the
Figure
IRET
PCH
PCL
stack
6.
SP
overflow.
or RSP
RET
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The