ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 67

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

SYNC PROCESSOR (SYNC) (Cont’d)
4.4.9 Corrector Mode
In this mode, you can perform the following
functions:
– Inhibit pre/post equalization pulses
– Extend VSYNCO pulse width by several scan
– Extend VSYNCO width during all post equaliza-
lines
tion pulses.
This removes all pre/post equalization pulses
on the HSYNCO signal.
The inhibition starts on the falling edge of
HSYNCO and lasts for (((HGENR+1)/4)-2)
µs. The decrease of 2µs (one minimum pulse
width) avoids the removal of the next pulse of
HSYNCO.
Procedure:
1. HSYNCO and VSYNCO polarities must be
2. Measure the low level of HSYNCO.
3. Set the 2FHINH bit in the CFGR register.
This function can be also used to extend the
video blanking signal.
Procedure:
1. HSYNCO and VSYNCO polarities must be
2. Set the 2FHINH bit in the CFGR register
3. The extension will be the number of
4. Reset the VCORDIS bit in the POLR
This function extends the VSYNCO pulse
width when post equalization pulses are
detected (2FHDET bit in the POLR register
and 2FHLAT bit in the LATR register).
positive.
only if some pre/post equalizations pulses
are detected. (2FHLAT, 2FHDET flags).
HSYNCO periods set in the VGENR
register.
register.
positive.
– Extend VSYNCO pulse width during pre and
Notes:
1. When corrector mode is active, the free-running
2. If VGENR=0, all VSYNCO correction functions
post equalization pulses (for test only).
This function allows extending the VSYNCO
pulse width as long as equalization pulses are
detected. (VSYNCO = VSYNCO + 2FHDET).
Procedure:
1. HSYNCO and VSYNCO polarities must be
2. Set the 2FHINH bit in the CFGR register to
3. Measure the low level of HSYNCO.
4. Update HGENR =(FFh - (HGENR + 1)) + 4.
5. Write VGENR > 0.
6. Reset the VCORDIS bit in the POLR register.
7. Set the VEXT bit in the CFGR register.
8. Set the 2FHEN bit in the ENR register.
frequencies generator and analyzer mode must
be disabled.
(HVGEN=0 in ENR register, HACQ=0, VACQ=0
in the CFGR register).
are disabled except the 2FHEN bit which must
be cleared if VGENR = 0 or VCORDIS = 1.
Procedure:
1. HSYNCO and VSYNCO polarities must be
2. Set the 2FHINH bit in the CFGR register to
3. Measure the low level of HSYNCO.
4. Update HGENR =(FFh - (HGENR + 1)) + 4
to add tolerance
5. Write VGENR > 0.
6. Reset the VCORDIS bit in the POLR
7. Set the VEXT bit in the CFGR register.
positive.
remove pre/post equalization pulses.
positive.
remove pre/post equalization pulses.
register
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