ST72T774J9B1 STMicroelectronics, ST72T774J9B1 Datasheet - Page 39

• Manufacturer Part Number: ST72T774J9B1
• Manufacturer: STMicroelectronics

Specifications of ST72T774J9B1

• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: I2C/USB
• Program Memory Type: EPROM
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• On-chip Adc: 1-chx8-bit
• On-chip Dac: 1-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 42
• Package Type: SPDIP
• Lead Free Status / Rohs Status: Specific Sites Compliant

4.2 WATCHDOG TIMER (WDG)
4.2.1 Introduction
The Watchdog timer is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which causes the application program
to abandon its normal sequence. The Watchdog
circuit generates an MCU reset on expiry of a
programmed time period, unless the program
Figure 26. Watchdog Block Diagram
4.2.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 49,152 machine
cycles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates a
reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR
register
at
f
CPU
regular
WDGA
intervals
RESET
T6
during
T5
WATCHDOG CONTROL REGISTER (CR)
7-BIT DOWNCOUNTER
normal
CLOCK DIVIDER
T4
49152
T3
refreshes the counter’s contents before the T6 bit
becomes cleared.
4.2.2 Main Features
operation to prevent an MCU reset. The value to
be stored in the CR register must be between FFh
and C0h (see
8
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
– The T5:T0 bits contain the number of increments
diate reset
which represents the time delay before the
watchdog produces a reset.
MHz)):
T2
Programmable timer (64 increments of 49152
CPU cycles)
Programmable reset
Reset (if watchdog activated) when the T6 bit
reaches zero
T1
Table 13 . Watchdog Timing (fCPU =
T0
ST72774/ST727754/ST72734
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