MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 103

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

2.3.2.6.5
Read: Anytime.
Write: Anytime.
2.3.2.6.6
Read: Anytime.
Write: Anytime.
Freescale Semiconductor
Module Base + 0x0034
Module Base + 0x0035
PERAD[7:0]
PPSAD[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
PERAD7
PPSAD7
Pull Device Enable Port AD — This register configures whether a pull-up or a pull-down device is activated, if
the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled.
It is not possible to enable pull devices when a associated ATD channel is enabled simultaneously.
0 Pull-up or pull-down device is disabled.
1 Either a pull-up or pull-down device is enabled.
Pull Select Port AD — This register selects whether a pull-down or a pull-up device is connected to the pin.
0 A pull-up device is connected to the associated port AD pin, if enabled by the associated bit in register PERAD
1 A pull-down device is connected to the associated port AD pin, if enabled by the associated bit in register
0
0
7
7
and if the port is used as input.
PERAD and if the port is used as input.
Port AD Pull Device Enable Register (PERAD)
Port AD Polarity Select Register (PPSAD)
PERAD6
PPSAD6
Figure 2-44. Port AD Pull Device Enable Register (PERAD)
0
0
6
6
Figure 2-45. Port AD Polarity Select Register (PPSAD)
Table 2-36. PERAD Field Descriptions
Table 2-37. PPSAD Field Descriptions
PERAD5
PPSAD5
MC9S12C-Family / MC9S12GC-Family
0
0
5
5
PERAD4
PPSAD4
Rev 01.24
0
0
4
4
Description
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
PERAD3
PPSAD3
0
0
3
3
PERAD2
PPSAD2
0
0
2
2
PERAD1
PPSAD1
0
0
1
1
PERAD0
PPSAD0
0
0
0
0
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