MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 458

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 15 Timer Module (TIM16B8CV1) Block Description
15.4.1
The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
458
PACLK/65536
PACLK/256
Bus Clock
PAOVF
Prescaler
INTERRUPT
REQUEST
PR[2:1:0]
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COMPARATOR
EDG0A
EDG1A
TCNT(hi):TCNT(lo)
PAOVF
PRESCALER
16-BIT COUNTER
PAOVI
CHANNEL2
CHANNEL 1
CHANNEL7
CHANNEL 0
PACNT(hi):PACNT(lo)
TC0
TC1
TC7
16-BIT COUNTER
EDG7A
EDG7B
EDG0B
EDG1B
INTERRUPT
PAOVI
LOGIC
PACLK/65536
PAOVF
PACLK/256
Figure 15-28. Detailed Timer Block Diagram
PACLK
CLEAR COUNTER
DETECT
DETECT
TE
DETECT
MC9S12C-Family / MC9S12GC-Family
EDGE
EDGE
EDGE
PAIF
C0F
C1F
C7F
PAI
PACLK
MUX
OM:OL1
OM:OL0
OM:O73
TOV1
TOV0
TOV7
CLK[1:0]
Rev 01.24
DIVIDE-BY-64
TOF
TOI
TEN
PEDGE
IOC0
CxF
CxI
C0F
C1F
PAE
IOC1
C7F
IOC7
INTERRUPT
LOGIC
IOC0 PIN
IOC1 PIN
IOC7 PIN
LOGIC
LOGIC
LOGIC
DETECT
EDGE
PAIF
channel 7 output
compare
TCRE
CH. 1 COMPARE
CH. 0 CAPTURE
CH. 1 CAPTURE
CH. 0COMPARE
CH. 7 COMPARE
CH.7 CAPTURE
PA INPUT
Freescale Semiconductor
Bus Clock
IOC0 PIN
IOC1 PIN
IOC7 PIN
TOF