MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 180
MC9S12C128VFU
Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12C128VFU.pdf
(690 pages)
Specifications of MC9S12C128VFU
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Chapter 6 Background Debug Module (BDMV4) Block Description
earlier. Synchronization between the host and target is established in this manner at the start of every bit
time.
Figure 6-7
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Because the host drives the high speedup pulses in these two cases, the rising edges look like digitally
driven signals.
The receive cases are more complicated.
system. Because the host is asynchronous to the target, there is up to one clock-cycle delay from the host-
generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
180
START OF BIT TIME
TARGET SYSTEM
TRANSMIT 1
TRANSMIT 0
PERCEIVED
CLOCK
HOST
HOST
shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
SYNCHRONIZATION
UNCERTAINTY
Figure 6-7. BDM Host-to-Target Serial Bit Timing
MC9S12C-Family / MC9S12GC-Family
Figure 6-8
10 CYCLES
Rev 01.24
TARGET SENSES BIT
shows the host receiving a logic 1 from the target
Freescale Semiconductor
EARLIEST
START OF
NEXT BIT
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