MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 140

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 4 Multiplexed External Bus Interface (MEBIV3)
4.3.2.7
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Data direction register E is associated with port E. For bits in port E that are configured as general-purpose
I/O lines, DDRE determines the primary direction of each of these pins. A 1 causes the associated bit to
be an output and a 0 causes the associated bit to be an input. Port E bit 1 (associated with IRQ) and bit 0
(associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of
whether the alternate interrupt function is enabled. The value in a DDR bit also affects the source of data
for reads of the corresponding PORTE register. If the DDR bit is 0 (input) the buffered pin input state is
read. If the DDR bit is 1 (output) the associated port data register bit state is read.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally. Also, it is not in the map in expanded modes while the EME control bit
is set.
140
Module Base + 0x0009
Starting address location affected by INITRG register setting.
Reset
DDRE
Field
7:2
W
R
Bit 7
Data Direction Port E
0 Configure the corresponding I/O pin as an input
1 Configure the corresponding I/O pin as an output
Note: It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from inputs to
Data Direction Register E (DDRE)
0
7
To ensure that you read the value present on the PORTE pins, always wait
at least one cycle after writing to the DDRE register before reading from the
PORTE register.
outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling
as outputs.
= Unimplemented or Reserved
6
0
6
Figure 4-11. Data Direction Register E (DDRE)
Table 4-5. DDRE Field Descriptions
MC9S12C-Family / MC9S12GC-Family
5
0
5
Rev 01.24
NOTE
4
0
4
Description
3
0
3
Bit 2
0
2
Freescale Semiconductor
0
0
1
0
0
0